Integrated circuit memories have become increasingly dense due to the need for increased memory storage. While fabrication techniques and design options have been fairly successful in maintaining steady increases in memory storage from design generation to generation, the need for new highly-populated circuits continues.
A dynamic random access memory (DRAM) device comprises an arrangement of individual memory cells. Each memory cell includes a capacitor capable of holding data as an electrical charge and an access transistor for accessing the charge stored on the capacitor. The charge is referred to as a data bit and its presence or absence on a storage capacitor produces either a high voltage or a low voltage, thereby representing data in a binary fashion. A high voltage corresponds to a "1" (i.e., a charged capacitor) and a low voltage corresponds to a "0" (i.e., an uncharged capacitor).
Data can be either stored to the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as bit lines, or digit lines, which are connected to input/output (I/O) lines through field-effect transistors (FETs) used as switching devices. In conventional DRAM architecture, a data bit's true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. Thus, each conventional memory cell has two associated digit lines: digit and digit complement. The digit line is coupled directly to a source/drain region of an access transistor for a particular memory cell.
Typically, memory cells are arranged in an array and each cell has an address identifying its location in the array. The array is a configuration of intersecting rows and columns, and a memory cell is associated with each intersection. In order to read from, or write to, a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a row decoder and to a column decoder. The row decoder activates a word line in response to the row address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The column decoder selects a digit line pair in response to the column address. For a read operation, the selected word line activates the access transistors for a given row address, and data is latched to a digit line.
Conventional dynamic memories use memory cells fabricated as capacitors in an integrated circuit to store data. That is, a logical "1" is stored as a charge on the capacitor and the capacitor is discharged for a logical "0". The pairs of digit lines are fabricated as metal, or silicided/polycided polysilicon, lines on the integrated circuit and connected to the memory cells for transmitting data stored in the memory cells. Sense amplifiers are utilized to sense small voltage differentials between a digit line and its complement. The sense amplifiers drive the digit lines to full power supply rails for either reading the memory cells, or writing thereto.
Although unique fabrication techniques and processes have been developed to reduce the size of the memory cells and access circuitry, the physical spacing requirements for the digit line architecture create a barrier to maximizing the available die area. That is, the reductions in memory cell size cannot be fully exploited due to the use of digit line pairs to read/write to a memory cell. Each individual digit line is highly capacitive, due to the large quantity of attached memory bits, the length of the line, and its proximity to other features. This capacitance dictates the design parameters of die circuitry. These problems are compounded due to the use of digit line pairs.
In the past, open digit line array architecture was most commonly used for DRAM circuitry, as shown in prior art FIG. 1. Such architecture is characterized by a memory cell located at each intersection between a word line and a digit line, or digit line complement. This type of architecture increases the chip density. However, several problems prevent such architecture from meeting the needs of highly dense ICs. Such problems include coupling between digit lines and high internal noise. Coupling between adjacent lines is inversely proportional to their spacing. As devices become smaller, the coupling problem becomes more pronounced.
Referring to prior art FIG. 1, a portion of a conventional dynamic memory access circuitry is described, showing an open digit line architecture. Memory arrays 100 have a plurality of memory cells 102, which are fabricated as capacitors having one capacitive plate connected to a reference voltage, or ground, at 104 and the other node connected to an access transistor 106. A typical reference voltage is one-half of the power supply voltage (Vcc). Each access transistor is a n-type transistor having its gate connected to a word line 108.
Digit lines 110 are each connected to a line of access transistors 106 and memory cells 102. When access transistors 106 are selectively activated, the charge stored on the corresponding memory cell 102 is coupled to the corresponding digit line 110. N-type isolation transistors 112 and 114 are used to selectively isolate digit lines 110 from the sense amplifiers 118 and bias circuitry. Bias circuits 116 are used to equalize the nodes of sense amplifiers 118 to the same voltage. The sense amplifiers 118 read the voltage difference between a pair of digit lines 110 to determine the logic of a memory cell 102. For example, a digit line 110 pair is shown in FIG. 1 as the digit line in column "A" and the digit line in column "B."
Alternatively, a folded digit line architecture was designed to improve noise immunity of such devices. Prior art FIG. 2 illustrates a portion of a memory array 200 having a folded digit line architecture. Folded digit line architecture is characterized by a memory cell 202 located at every other digit line 210/word line 208 intersection. A memory array 200 has a plurality of memory cells 202 which are fabricated as capacitors having one capacitive plate connected to a reference voltage, or ground, at 204 and having the other node connected to an access transistor 206. A typical reference voltage is one-half of the power supply voltage (Vcc). Each access transistor 206 is a n-type transistor having its gate connected to a word line 208(0)-(n).
Digit lines 210 are connected to access transistors 206 and memory cells 202. When access transistors 206 are selectively activated, the charge stored on the corresponding memory cell 202 is coupled to the digit line 210. The sensing implementation and other related components are similar to those described in prior art FIG. 1. N-type isolation transistors 212 and 214 are used to selectively isolate digit lines 210 from the sense amplifier 218 and bias circuitry 216. Bias circuit 216 is used to equalize the nodes of the sense amplifier 218 to the same voltage. The sense amplifier 218 reads the voltage difference between a pair of digit lines 210. The digit line 210 pair for any of the memory cells 204 shown in FIG. 2 is the two digit lines 210 in columns "A" and "B."
This type of architecture does not provide the same degree of packing density seen in the open digit line architecture described above. Its packing density is approximately twenty-five-percent lower than in the open digit line architecture. However, noise immunity of the integrated circuit is improved using folded digit line architecture over the open digit line architecture.
Plan views of the open digit line architecture and the folded digit line architecture are shown, respectively, in prior art FIGS. 3 and 4. FIG. 3 shows a memory cell 302 located at each intersection between a word line 308 and a digit line 310. Digit lines 310 run perpendicular to the word lines 308. Digit line interconnects 330 connect underlying source/drain regions of access transistors to digit lines 310.
FIG. 4 shows a memory cell 402 located at every other intersection between a word line 408 and a digit line 410. Digit lines 410 run perpendicular to the word lines 408. Digit lines 410 make connections to underlying source/drain regions of access transistors at interconnects 430.
While the layout of a folded bit architecture of FIG. 4 is not as efficient as that in FIG. 3, the noise immunity of the circuit is improved, over the open bit architecture of FIG. 3. The continued decrease in device size makes using an open digit line architecture, such as that in FIG. 3, problematic, due to coupling between digit line 310 pairs. Folded digit line architecture does not perfect such coupling problems, however. Recently, the trend in fabricating integrated circuit memories includes twisting adjacent digit line pairs to improve signal-to-noise characteristics. Such twisting is undesired because it occupies valuable silicon area. As devices are becoming more dense, silicon area is becoming more scarce.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a DRAM architecture, having a higher packing density, which allows for more densely populated memories, and less coupling between digit lines. This must be accomplished while maintaining, or lowering, the noise immunity present in the folded digit line architecture.